The present invention relates to a semiconductor device, and can be used appropriately for a semiconductor device having, e.g., an active element (component) in a wiring layer.
A technique which provides an active element (component) in a wiring layer in a semiconductor device has been known. The active element (component) allows the function of such a semiconductor device to be changed without involving a change in the layout of semiconductor elements formed over a semiconductor substrate. Therefore, it is possible to manufacture a plurality of types of semiconductor devices having different functions using the semiconductor substrate, while keeping the same layout of the semiconductor elements over the semiconductor substrate. In this case, the manufacturing cost of the semiconductor devices can be reduced.
For example, a semiconductor device and a manufacturing method of the semiconductor device are disclosed in Japanese Unexamined Patent Publication No. 2010-141230 (corresponding US Patent Application Publication No. 2010/148171 (A1)). The semiconductor device includes a semiconductor substrate, a first wiring layer, a semiconductor layer, a gate insulating film, and a gate electrode. The first wiring layer includes an insulating layer formed over the semiconductor substrate, and first wires embedded in the surface of the insulating film. The semiconductor layer is located over the first wiring layer. The gate insulating film is located over or under the semiconductor layer. The gate electrode is located on the opposite side of the semiconductor layer via the gate insulating film. At this time, the semiconductor layer, the gate insulating film, and the gate electrode form a transistor as an active element (component). It is possible to use, e.g., one of the first wires as the gate electrode. It is also possible to use, e.g., a diffusion preventing film in the first wiring layer as the gate insulating film. In that case, the gate insulating film is formed under the semiconductor layer. The semiconductor device has a so-called bottom-gate element structure. The semiconductor device can further include a charge trap film, and a back-gate electrode over the semiconductor layer. In this case, the semiconductor device basically has a bottom-gate element structure, which is a double-gate element structure auxiliarily also including the gate opposing the bottom gate.
As a related-art technology, a technique for a semiconductor device is disclosed in Japanese Unexamined Patent Publication No. 2009-94494 (corresponding US Patent Application Publication No. 2009/078970 (A1)). In the semiconductor device, over a substrate having an insulating surface, a plurality of field effect transistors are stacked with respective interlayer insulating layers interposed therebetween. The semiconductor layers included in the plurality of field effect transistors are isolated from each other by the semiconductor substrate. The semiconductor layers are joined with the substrate having the foregoing insulating surface or with respective insulating layers provided over the foregoing interlayer insulating layers. The plurality of field effect transistors are each covered with an insulating film which gives a strain to each of the semiconductor layers.
A manufacturing method of a semiconductor device, the semiconductor device, an electrooptical device, and an electronic device are disclosed in Japanese Unexamined Patent Publication No. 2009-283819. In the manufacturing method of the semiconductor device, a plurality of semiconductor films are laminated. The manufacturing method of the semiconductor device includes five steps. The first step is the step of forming a plug electrode including carbon nanotube over the first semiconductor film. The second step is the step of forming an interlayer insulating film around the formed plug electrode. The third step is the step of planarizing the surface of the interlayer insulating film to expose the top portion of the plug electrode. The fourth step is the step of forming the amorphous second semiconductor film over the interlayer insulating film and the top portion of the plug electrode. The fifth step is the step of supplying energy to the amorphous second semiconductor film to cause the exposed plug electrode to function as a catalyst and crystallize the amorphous second semiconductor film.
As a related-art technology, an LSI is disclosed in Non-Patent Document 1 (2012 Symposium on VLSI Technology digest of Technical Papers, 123-124 (2012)) in which an oxide semiconductor layer is incorporated in a multilayer interconnect layer. Also, as a related-art technology, a CMOS circuit using an oxide semiconductor layer is disclosed in Non-Patent Document 2 (2011 Symposium on VLSI Technology Digest of Technical Papers, 120-121 (2011)). Also, as a related-art technology, a transistor device structure using an oxide semiconductor layer is disclosed in Non-Patent Document 3 (2011 IEEE International Electron Devices Meeting (IEDM), 155-158 (2011)).